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[Other] da_fir

Description: 基于verilog的分布式算法FIR滤波器 有两个文件 一个用来生成查找表-FIR filter using Distributed Algorithm.
Platform: | Size: 2048 | Author: 小关 | Hits:

[VHDL-FPGA-Verilog] fir

Description: 用Verilog语言设计的一个数字FIR低通滤波器，很实用，通过modelsim仿真成功-Verilog language to design a digital FIR low-pass filter, very practical, through modelsim simulation success
Platform: | Size: 1685504 | Author: liu | Hits:

[Other] FIR

Description: 一个不错的数字滤波器verilog源码，希望大家能用的上-A good digital filter verilog source
Platform: | Size: 12288 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] my_fir

Description: Verilog 写的FIR滤波器，modelsim仿真通过-Verilog write FIR filter, modelsim simulation through
Platform: | Size: 1024 | Author: 韩帅 | Hits:

[VHDL-FPGA-Verilog] filter_signed_and_unsigned

Description: FIR滤波器的verilog语言实现（输入为8bit有符号以及无符号两种，滤波器为8阶，截止频率约在6*pi/7）-FIR filter verilog language (input 8bit signed and unsigned are two 8-order filter cut-off frequency is about 6* pi/7)
Platform: | Size: 3072 | Author: 范慧敏 | Hits:

[Other] proiect

Description: Fir filter implemented in verilog and tasted. also conteins the implementation in simulink
Platform: | Size: 1844224 | Author: valentina199114 | Hits:

[VHDL-FPGA-Verilog] fir_filter_50Mhz

Description: 基于并行分布式算法的高速Fir滤波器的设计代码，采用Verilog编写，压缩包为quartus II编译过的工程代码-Parallel and distributed algorithms based on a high-speed Fir filter design code, Verilog prepared, compressed package for the quartus II compiled project code
Platform: | Size: 8773632 | Author: Eason | Hits:

[VHDL-FPGA-Verilog] FIR_FILTER

Description: FIR滤波器的verilog实现，包含testbench，以及设计文档，文档里面详细介绍了滤波器系数的求取-FIR filter verilog implementation, including testbench, and the design document, the document which details the filter coefficients to strike
Platform: | Size: 14336 | Author: 雷 | Hits:

[VHDL-FPGA-Verilog] FIR_dida

Description: 自己写的FIR滤波器设计，verilog语言写的，很好用-Write your own FIR filter design, verilog language, easy to use
Platform: | Size: 1504256 | Author: chenshuo | Hits:

[Other Embeded program] FIRverilog

Description: 多种FIR滤波器的verilog语言实现 (数字信号处理的FPGA实现)-Verilog language variety FIR filter implementation (digital signal processing FPGA implementation)
Platform: | Size: 8192 | Author: 宋俊 | Hits:

[Other] fir4btp

Description: 4tap FIR filter in verilog code
Platform: | Size: 1024 | Author: pravat | Hits:

[VHDL-FPGA-Verilog] fir16.v

Description: 16阶FIR滤波器设计的verilog代码-Verilog 16-order FIR filter
Platform: | Size: 1024 | Author: lijinpeng | Hits:

[VHDL-FPGA-Verilog] fir48

Description: 48阶FIR滤波器的verilog，包含测试文件-48-order FIR filter verilog, including test paper
Platform: | Size: 2048 | Author: lijinpeng | Hits:

[VHDL-FPGA-Verilog] FIR

Description: FPGA设计在设计过程中使用ISE软件自带的IP核时，消耗资源太大的时候，需要自己编写滤波器的源代码，这里给出我们常用的串行FIR核的verilog语言代码设计文件，并通过作者时序仿真验证，并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code of the filter, presented here we commonly used serial FIR the verilog language code design document, and through the author timing simulation, and used for actual projects
Platform: | Size: 6000640 | Author: lirui | Hits:

[Other] low_pass-filter-design

Description: 基于Verilog的fir低通数字滤波器-Verilog-based fir low pass digital filter
Platform: | Size: 719872 | Author: SamHillzj | Hits:

[VHDL-FPGA-Verilog] firfilterverilog

Description: FIR FILTER DESIGNED IN VERILOG FOR 4 BIT MULTIPLIER
Platform: | Size: 143360 | Author: neha | Hits:

[DSP program] book3e

Description: 数字信号处理的FPGA实现随书光盘，包含大量Verilog代码，包括加法器，乘法器以及FIR滤波器设计，快速傅立叶变换-FPGA digital signal processing to achieve the CD with the book, contains a large amount of Verilog code, including the adder, multiplier and FIR filter design, fast Fu Liye transform
Platform: | Size: 1870848 | Author: 刘许军 | Hits:

[VHDL-FPGA-Verilog] FIRfilterverilogHDL

Description: FIR滤波器的verilog HDL代码示例，以16阶为例-Verilog HDL code for fir filter
Platform: | Size: 1024 | Author: L Liu | Hits:

[matlab] filter_FIR

Description: fir filter is made in the verilog
Platform: | Size: 4096 | Author: dharmen | Hits:

[assembly language] FIR_16bits_LP

Description: This is a verilog code for Low pass FIR Filter which inputs 16bit wide.
Platform: | Size: 2048 | Author: rohit | Hits:
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